The present invention regards a process for forming a buried cavity in a semiconductor material wafer.
As is known, the possibility of manufacturing RF integrated circuits in CMOS or BiCMOS technology would make it possible to obtain lower consumption and lower costs as compared to normal circuits made using gallium arsenide (GaAs).
At present, however, this possibility is limited by the poor efficiency of the passive elements, and in particular by the inductors, on account of the high parasitic capacitances of the substrate which give rise to low resonance frequencies and preclude the use of high-frequency inductors, and on account of the high conductivity of the substrate, which markedly limits the quality factor Q of the inductor.
Typical values of the quality factor Q for integrated inductors made on GaAs are of the order of 20 for frequencies of 2 GHz, whereas values of the quality factor Q smaller than 5 are obtained for inductors integrated on high-conductivity silicon substrates (CMOS processes).
To increase the quality factor Q of integrated inductors in the entire range of interest it is important to reduce both the losses due to the metallizations that make up the coil and losses due to the substrate.
The losses due to metallizations can be reduced by using aluminum or copper thick layers having relatively high electrical conductivity. However, the skin effect, which, for example, for copper is of the order of 1.5 xcexcm at a frequency of 1 GHz, limits the thickness of the metallization layer in which the current effectively flows. It follows therefore that there is no point in using metallization regions having a thickness of over 2 xcexcm to seek to increase the inductor quality factor Q.
The losses due to the substrate can be reduced by using high-resistivity substrates. However, this solution is not compatible with CMOS technology, which enables only low-resistivity substrates to be obtained.
One of the techniques used to reduce the losses due to the substrate envisages the formation of a thick oxide layer, namely of over 60 xcexcm, underneath the inductor, which limits the currents inductively generated in the substrate, thus improving the inductor quality factor Q and at the same time enabling higher resonance frequencies to be obtained and wider metallization strips to be used, in this way also reducing ohmic dissipation.
This technique is schematically illustrated in FIGS. 1a-1c and envisages the formation, in a wafer 1 of monocrystalline silicon, of deep trenches 2 (FIG. 1a), complete thermal oxidation of the columns 3 of silicon comprised between each pair of contiguous trenches 2 (FIG. 1b), and then chemical vapor deposition (CVD) of a layer of TEOS 4 (tetraethyl orthosilicate), the purpose of which is to complete filling of the trenches and to prepare the surface of the substrate (planarization) for the subsequent forming of the inductor (FIG. 1c).
This technique is, however, very costly in that it requires a long time for forming the trenches (1 xcexcm/min) and moreover with current etching machines it is not possible to carry out the operation simultaneously on a number of wafers, but only on a single wafer at a time.
An alternative technique that has been proposed recently and that makes it possible to reduce losses due to the substrate is described in xe2x80x9cPROCEEDINGS OF THE IEEE,xe2x80x9d vol. 86, No. 8, August 1998, page 1632, and essentially envisages the creation of a cavity or air gap underneath the inductor by removing the silicon underneath the inductor by means of anisotropic chemical etches made using potassium hydroxide (KOH), tetramethyl ammonium hydroxide (TMAH), etc., and employing a sacrificial polycrystalline-silicon layer.
This technique is schematically illustrated in FIGS. 2a-2c, and essentially involves the deposition and definition, using a special mask, of a sacrificial polycrystalline-silicon layer 5 on the top surface of the substrate 1, deposition of a silicon-nitride (Si3N4) layer 6 above the sacrificial polycrystalline-silicon layer 5 (FIG. 2a), and then the carrying-out of an anisotropic etch of the substrate 1 through an opening 7 made in the silicon-nitride layer 6 (FIG. 2b). By means of the anisotropic etch, the sacrificial polycrystalline-silicon layer 5 and part of the substrate 1 are thus removed, and a cavity or air-gap 8 is obtained having a roughly triangular cross section, which is separated from the outside environment by a diaphragm 9 consisting of the portion of the silicon-nitride layer 6 overlying the cavity 8, and on which the inductor can subsequently be made.
This technique presents some drawbacks that do not enable adequate exploitation of all its advantages.
In the first place, for the formation of the cavity 8 the above technique requires the deposition, and the corresponding definition through a special mask, of a sacrificial polycrystalline-silicon layer 5, with the costs associated thereto.
In the second place, the said technique does not enable a uniform isolation level to be obtained underneath the inductor, in that isolation is maximum at the center of the cavity 8 (i.e., at the vertex that is set further down of the triangle) whilst it is minimum at the ends of the cavity 8 (i.e., at the two vertices of the triangle that are set higher up). Consequently, in order to guarantee a minimum level of isolation of the inductor that may be acceptable over the entire extent of the latter, it is typically necessary to provide a cavity, the top area of which is larger than the area of the inductor, with a consequent larger area occupied on the silicon with respect to the one that would be occupied if the known technique illustrated in FIGS. 1a-1c were instead used.
According to the principles of the invention, a buried cavity is formed in a semiconductor material wafer. A mask is formed on the surface of the semiconductor material wafer. There is, in the mask, a lattice region. The lattice region has a plurality of openings or holes that are generally square or rectangular in shape. The lattice is oriented to a line that is inclined at between 30xc2x0 and 60xc2x0 with respect to a particular crystallographic plane of the wafer.
The wafer is anisotropically etched, such that cavities form under the holes in the lattice region of the mask. as the etch runs under the mask in a direction parallel to a crystallographic plane of the substrate, the holes join together to form a single cavity under the lattice region of the mask. The top and bottom walls of the cavity are substantially parallel, while the side walls slope inward from the top. A chemical vapor deposition is carried out, forming a TEOS layer, which completely closes the openings in the mask, resulting in a thin wall or diaphragm above a sealed cavity.